Each device can report its power consumption. Leave a Comment Please sign in to add a comment. If the power limit is still exceeded at the “maximum efficiency” frequency typically 1. Add class driver PowerCap: Soon it is very likely that other vendors are also adding or considering such implementation.

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Log in to post comments. Capoing each device can be constrained to some power, extra power can redistributed to other devices, which needs additional performance.

I seem to recall one case with severe thermal throttling that was running very slowly as if duty cycle modulation was being employedbut I never saw any changes to the corresponding MSRs. Each device can report its power consumption. Power capping must have done differently among these intl kinds of applications.

Power Capping Framework and RAPL Driver []

Fri, 4 Oct Skip to main content. I can conform your observation with compute-bound applications.

Leave a Comment Please sign in to add a comment. Intel is slowly adding many devices under RAPL control. Where can i find official information? Article Overview With the ppwer of technologies, which enables power monitoring and limiting, more and more devices are able to constrain their power consumption under certain limits.


Hello, i’m looking at performance variations of my application under a range of power caps.

RAPL power capping: how does it work

It is easy enough to monitor the actual unhalted processor cycles to determine the average frequency. At least some processors will support frequencies below the “maximum efficiency” frequency, but I don’t know if the Power Control Unit will use these or switch to duty cycle modulation Section If the power limitation is low, it manipulates clock duty cycles.

Depending on your processor, another place to look for DVFS is in the “uncore” clock. While staying below a power limit, it allows devices to automatically adjust performance to meet demands – Dynamic control and re-budgeting: I read through the two sections in the manual, still I’m not very clear what is the difference between duty cycle modulation and clock cycle modulation?

Add class driver PowerCap: With a low power cap, the perfromance is very bad. Someone told me, if the power cap is high, it does DVFS. Setting DVFS to 1. Power Capping framework is an effort to have a uniform interface available to Linux drivers, which will enable – A uniform sysfs interface for all devices which can offer power capping – A common API for drivers, which will avoid code duplication and easy implementation of client drivers.


One possible interpretation is that the MSRs show software-controlled duty-cycle modulation, but may not show hardware-initiated duty-cycle modulation. Soon it is very likely that other vendors are also adding or considering such implementation. In one instance, I noticed that when running a power-limited application on a Xeon Platinum system, the uncore frequency was reduced by a much larger percentage than the core frequency.

My questions is how RAPL caps the power. For more complete information about compiler optimizations, see our Optimization Notice. Changes in retired instruction rate may indicate hardware clock cycle modulation. I checked duty cycling and clock modulation.

RAPL power capping: how does it work

With a high power cap, the performance is reasonable. If power cap is set to 45 watts no DVFS and turbo boost is onthe observed frequency is more or less 1. Added to drivers build bitops: There are several use cases for such technologies: